With circuits of this kind for clock and/or data recovery or CDR circuits a difference is made, in the main, between the type of phase detector and the type of voltage-controlled oscillator, as follows:                linear phase detector:        the linear phase difference at both inputs of the phase detector is indicated at the output of the phase detector;        binary phase detector:        if a bit change takes place at the data input, the plus/minus sign of the phase difference of the two inputs (clock and/or data) of the phase detector is ascertained (leading or trailing) at the output of the phase detector; this may be indicated, for example, by two digital phase detector output signals: “up” (for leading) and “down” (for trailing); for binary phase detectors the Alexander phase detector known from the state of the art is very frequently used (see FIG. 1—possible circuit for implementing a half-rate Alexander phase detector).        
CDR circuits with Alexander phase detector are frequently used for data transmissions in a frequency range greater than one Gigahertz, for they are easier to implement for a limited speed of the used technology and show a very robust behaviour (better so-called power supply rejection).
For high input data rates of more than one Gigahertz the necessary logic blocks of the phase detector are normally implemented in C[urrent]M[ode]L[ogic]. FIG. 2 shows the implementation of a flip-flop in the form of two latch blocks, FIG. 3 shows the implementation of a latch with resistivew load (so-called R-load) in C[urrent]M[ode]L[ogic], wherein the output impedance is normally implemented by discrete poly resistances.
When implementing CDR applications, where a low output jitter of the generated output clock is required, a voltage-controlled LC oscillator (VCO) is frequently used, not least because of its inherent low phase noise. Disadvantageous with this conventional type of circuit are a small tuning range and a relatively large chip surface for the implementation of the coil L on the chip.
When implementing CDR applications, where a wide tuning factor is required, a voltage-controlled ring oscillator (VCO) is frequently used. Disadvantageous with this conventional type of circuit is the output jitter, which is higher compared to the LC oscillator due to the higher phase noise of the ring oscillator. Here too, as with the phase detector for frequencies of more than one Gigahertz, the ring oscillator is usually implemented as a CML.
FIG. 4 shows a ring oscillator which is implemented in the form of four voltage-controlled oscillator buffer stages VCB and which automatically generates two clocks CLKI and CLKQ each of which comprise a phase shift of ninety degrees. The generation of CLKI and CLKQ is advantageous when implementing a half-rate phase detector.
FIG. 5 shows a possible implementation of a voltage-controlled oscillator buffer stage VCB with resistive output load (so-called R-load), wherein the frequency of the ring oscillator can be altered via a variation of the voltage at the pins VBNF and VBNS, by a factor of about 2.5. For a higher variation of the frequency of the oscillator (data rate), for example by a factor of 5, a divider (N=2) may be optionally connected at the output of the oscillator.
The disadvantages of the conventional solutions described according to the examples of FIG. 1 to FIG. 5 are, on the one hand, a high power consumption due to the necessity of an additional divider circuit (N=2) for lower data rates; on the other, these conventional solutions are not suitable for scaling the power loss of the clock and/or data recovery (CDR) with the data rate.